1. Technical Field
The present invention relates to a video signal processing integrated circuit (IC) and an IC designing method and, more particularly, to a method for designing a de-emphasis circuit for a video signal processing IC in order to reduce operating steps and material costs by minimizing the number of components of external application circuits of a de-emphasis output terminal of the video signal processing IC, and to an IC made by the method.
2. Related Art
A typical video cassette recorder (VCR) playback circuit includes a video head 110, a rotary transformer, a pre-amplifier, and a video signal processing IC. In the playback (PB) mode, a modulated video signal is detected by the video head, is input to the pre-amplifier via the rotary transformer for amplification with a predetermined gain, and is then input to the video signal processing IC which blocks a low-frequency component color signal among the signals input thereto and allows a frequency-modulated (FM) luminance signal having a high-frequency component to pass through. The high-pass filtered FM luminance signal is demodulated, and the demodulated luminance signal is subject to high-frequency component noise reduction and is then applied to a de-emphasis unit.
The de-emphasis unit compensates the demodulated luminance signal so that it has a frequency characteristic of the luminance signal before recording. The PB video level varies according to a gain which is set during manufacture of the video signal processing IC. Since the gain is set by means of a resistor having a certain value, an error in the PB level may be generated in the actual manufacturing process depending on deviation in the value of the resistor.
As described above, the video signal processing IC is designed such that a variable resistor or fixed resistor is necessarily added to the de-emphasis output pin port of the video signal processing IC. This increases the number of components, thereby lowering the manufacturing efficiency, increasing the cost of the product, and causing a deviation in the PB level due to resistance variation of the fixed resistor on the exterior of the IC.